1. Field of Invention
The present invention relates to semiconductor fabrication. More particularly, the present invention relates to a method for forming a deep trench capacitor under a shallow trench isolation structure, suitable for use in a dynamic random access memory (DRAM) device.
2. Description of Related Art
As the dimension of semiconductor device is more and more reduced, such as the fabrication generation of 0.15 microns or less, a DRAM device usually would take a deep trench capacitor formed in the semiconductor substrate to provide the memory function. The deep trench capacitor usually is also formed under a shallow trench isolation structure. The deep trench capacitor has already been widely used in the conventional DRAM. However, since the deep trench capacitor is formed under the shallow trench isolation structure, it needs several times of photomask fabrication, so as to performing etching. How to reduce the use of photomask for reducing the complexity in fabrication is a key issue needed to be considered in device design.
FIGS. 1A-1D are cross-sectional views, schematically illustrating a conventional method to fabricate a deep trench capacitor. In FIG. 1A, a substrate 100 is provided. A pad oxide layer 102, a silicon nitride layer 104, and a photoresist layer 106 are sequentially formed on the substrate 100. The photoresist layer 1106 has an opening 102 to expose the silicon nitride layer 104. Using the opening, the silicon nitride layer 104, the pad oxide layer 102 and the substrate 100 are etched, whereby a deep trench 107 is formed in the substrate. The deep trench usually is about 7-8 microns.
In FIG. 1B, a deep trench capacitor is formed at the lower portion of the deep trench 107. The deep trench capacitor includes a buried plate 108 diffused into the substrate 100, a capacitor dielectric 110, and a polysilicon electrode 112. An oxide collar 114 is formed on a sidewall of the deep trench 107 at the portion above the capacitor. A polysilicon layer fills into the deep trench 107 above the capacitor. The polysilicon layer includes a lower portion between the oxide collar 114 and an upper portion 118 which has a contact to the deep trench. An implantation process with sufficient energy is performed is performed to implant ions into the substrate o as to form a buried plate 120. The buried electrode 120 also has an electric contact on the buried plate 108. Moreover, the polysilicon layer 116, 118 are also implanted with dopants.
In FIG. 1C, The dopants of the polysilicon layer 116, 118 can diffuse into the substrate surface to form a diffusion extension region 124 by a thermal process. The diffusion extension region 124 is used for a connection to a source/drain region of metal-oxide semiconductor (MOS) transistor formed later. At this stage, the trench capacitor 108+110+112 is electrically coupled to the subsequently formed device through the polysilicon layer 116, 118 and the diffusion extension region 124. However, the adjacent two trench capacitors are necessary to be isolated, usually, by a shallow trench isolation (STI) structure. Therefore, it is necessary to form an opening 122. Formation of the opening 122 conventionally needs another photolithography and etching process, so as to properly remove portions of the silicon nitride layer 104, the pad oxide layer 102, the substrate 100, and the polysilicon layer 118. This needs an additional fabrication of photomask and the associated photoresist layer.
In FIG. 1D, a shallow trench isolation structure 126 is formed to fill the shallow trench isolation opening 122. Remaining portions of the silicon nitride layer 104 and the pad oxide layer 102 are removed. A MOS transistor is then formed, where the source/drain region 130 is coupled to the diffusion region 124.
In the foregoing conventional method, the STI structure 126 needs the additional photomask, causing more fabrication complexity and higher fabrication cost.